Figure 69. Capture/Compare Channel (Example: Channel 1 Input Stage); Figure 70. Capture/Compare Channel 1 Main Circuit - STMicroelectronics STM32F05 series Reference Manual

Advanced-control timers (TIM1)

Figure 69. Capture/compare channel (example: channel 1 input stage)

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 70. Capture/compare channel 1 main circuit

read CCR1H
read CCR1L
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIM1_EGR
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TI1
TI1F
filter
f downcounter
DTS
ICF[3:0]
TIMx_CCMR1
S
read_in_progress
Capture/compare preload register
R
capture_transfer
input
mode
Capture/compare shadow register
Doc ID 018940 Rev 1
TI1F_Rising
0
TI1FP1
Edge
Detector
TI1F_Falling
1
CC1P/CC1NP
TIMx_CCER
TI2F_rising
0
(from channel 2)
TI2F_falling
1
(from channel 2)
APB Bus
MCU-peripheral interface
8
8
compare_transfer
capture
Counter
TI1F_ED
to the slave mode controller
01
TI2FP1
IC1
divider
10
/1, /2, /4, /8
TRC
11
(from slave mode
controller)
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
write CCR1H
S
write_in_progress
write CCR1L
R
output
mode
UEV
(from time
comparator
base unit)
CNT>CCR1
CNT=CCR1
RM0091
IC1PS
CC1E
TIMx_CCER
CC1S[1]
CC1S[0]
OC1PE
OC1PE
TIM1_CCMR1