Timer Synchronization; Figure 130. Control Circuit In External Clock Mode 2 + Trigger Mode; Figure 131. Master/Slave Timer Example - STMicroelectronics STM32F05 series Reference Manual

RM0091

Figure 130. Control circuit in external clock mode 2 + trigger mode

Counter clock = CK_CNT = CK_PSC
16.3.15

Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 131: Master/Slave timer example
the master mode selection blocks.
Using one timer as prescaler for another

Figure 131. Master/Slave timer example

Clock
Prescaler
For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Figure 131. To do this:
●
Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
●
To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in
slave mode using ITR1 as internal trigger. You select this through the TS bits in the
TIM2_SMCR register (writing TS=000).
●
Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the
periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).
●
Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer 2.
TI1
CEN/CNT_EN
ETR
Counter register
TIF
TIM1
MMS
Master
UEV
TRGO1
mode
control
Counter
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
34
presents an overview of the trigger selection and
TS SMS
Slave
CK_PSC
ITR1
mode
control
Input
trigger
selection
35 36
TIM2
Counter
Prescaler
323/742