Usart Registers; Control Register 1 (Usart_Cr1) - STMicroelectronics STM32F05 series Reference Manual

RM0091
25.7

USART registers

Refer to
25.7.1

Control register 1 (USART_CR1)

Address offset: 0x00
Reset value: 0x0000
31 30 29
Res Res Res
15 14 13
OVER
CMIE MME
8
rw rw rw
Bits 31:28 Reserved, must be kept at reset value
Bit 27 EOBIE: End of Block interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated when the EOBF flag is set in the USART_ISR register
Note: If the USART does not support Smartcard mode, this bit is reserved and forced by
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time,
depending on the oversampling rate)
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
This bit field can only be written when the USART is disabled (UE=0).
Bits 20:16 DEDT[4:0]: Driver Enable deassertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted message,
and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8
or 1/16 bit time, depending on the oversampling rate).
If the USART_TDR register is written during the DEDT time, the new data is transmitted only
when the DEDT and DEAT times have both elapsed.
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept
This bit field can only be written when the USART is disabled (UE=0).
Universal synchronous asynchronous receiver transmitter (USART)
Section 1.1 on page 34
28 27 26 25
Res EOBIE RTOIE
rw rw rw
12 11 10 9
M WAKE PCE PS
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hardware to '0'. Please refer to
forced by hardware to '0'.
cleared. Please refer to
cleared. Please refer to
Doc ID 018940 Rev 1
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
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8 7 6
RXNEI
PEIE TXEIE TCIE
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Section 25.4: USART implementation on page
Section 25.4: USART implementation on page
Section 25.4: USART implementation on page
Section 25.4: USART implementation on page
21 20 19 18
DEDT[4:0]
rw rw rw rw
5 4 3 2
IDLEIE TE RE
E
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17 16
rw rw
1 0
UESM UE
rw rw
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573.
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