STMicroelectronics STM32F05 series Reference Manual page 630

Universal synchronous asynchronous receiver transmitter (USART)
Bit 12 EOBCF: End of timeout clear flag
Note: If the USART does not support Smartcard mode, this bit is reserved and forced by
Bit 11 RTOCF: Receiver timeout clear flag
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
Bit 10
Bit 9 CTSCF: CTS clear flag
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
Bit 8 LBDCF: LIN break detection clear flag
Note: If LIN mode is not supported, this bit is reserved and forced by hardware to '0'. Please
Bit 7
Bit 6 TCCF: Transmission complete clear flag
Bit 5 Reserved, must be kept at reset value.
Bit 4 IDLECF: Idle line detected clear flag
Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
Bit 3 ORECF: Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the USART_ISR register.
Bit 2 NCF: Noise detected clear flag
Writing 1 to this bit clears the NF flag in the USART_ISR register.
Bit 1 FECF: Framing error clear flag
Writing 1 to this bit clears the FE flag in the USART_ISR register.
Bit 0 PECF: Parity error clear flag
Writing 1 to this bit clears the PE flag in the USART_ISR register.
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Writing 1 to this bit clears the EOBF flag in the USART_ISR register.
hardware to '0'. Please refer to
Writing 1 to this bit clears the RTOF flag in the USART_ISR register.
forced by hardware to '0'. Please refer to
page 573.
Reserved, must be kept at reset value.
Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.
hardware to '0'. Please refer to
Writing 1 to this bit clears the LBDF flag in the USART_ISR register.
refer to Section 25.4: USART implementation on page
Reserved, must be kept at reset value.
Writing 1 to this bit clears the TC flag in the USART_ISR register.
Doc ID 018940 Rev 1
Section 25.4: USART implementation on page
Section 25.4: USART implementation on
Section 25.4: USART implementation on page
573.
RM0091
573.
573.