Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
7.4.5

APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
DAC PWR
CECR
Res
ST
RST RST
rw rw
15 14 13
SPI2
Res Res Res
RST
rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 CECRST HDMI CEC reset
Set and cleared by software.
0: No effect
1: Reset HDMI CEC
Bit 29 DACRST: DAC interface reset
Bit 28 PWRRST: Power interface reset
Bits 27:23 Reserved, must be kept at reset value.
Bit 22 I2C2RST: I2C2 reset
Bit 21 I2C1RST: I2C1 reset
Bits 20:18 Reserved.
Bit 17 USART2RST: USART2 reset
Bits 16:15 Reserved, must be kept at reset value.
28 27 26 25
Res Res Res
rw
12 11 10 9
WWD
Res Res
GRST
rw
Set and cleared by software.
0: No effect
1: Reset DAC interface
Set and cleared by software.
0: No effect
1: Reset power interface
Set and cleared by software.
0: No effect
1: Reset I2C2
Set and cleared by software.
0: No effect
1: Reset I2C1
Set and cleared by software.
0: No effect
1: Reset USART2
Doc ID 018940 Rev 1
24 23 22 21
I2C2 I2C1
Res Res
RST RST
rw rw
8 7 6 5
TIM14
Res Res Res
RST
rw
Reset and clock control (RCC)
20 19 18
USART
Res Res Res
RST
4 3 2
TIM6 TIM3
Res Res
RST RST
rw
17 16
2
Res
rw
1 0
TIM2
RST
rw rw
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