Figure 254. Full-Duplex Single Master/ Single Slave Application; Figure 255. Half-Duplex Single Master/ Single Slave Application - STMicroelectronics STM32F05 series Reference Manual

RM0091
and the MISO pins. During SPI communication, data is shifted synchronously on the SCK
clock edges provided by the master. The master transmits the data to be sent to the slave
via the MOSI line and receives data from the slave via the MISO line. When the data frame
transfer is complete (all the bits are shifted) the information between the master and slave is
exchanged.

Figure 254. Full-duplex single master/ single slave application

1. The NSS pin is configured as an input in this case.
Half-duplex communication
The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the
SPIx_CR1 register. In this configuration, one single cross connection line is used to link the
shift registers of the master and slave together. During this communication, the data is
synchronously shifted between the shift registers on the SCK clock edge in the transfer
direction selected reciprocally by both master and slave with the BDIOE bit in their
SPIx_CR1 registers. In this configuration, the master's MISO pin and the slave's MOSI pin
are free for other application uses and act as GPIOs.

Figure 255. Half-duplex single master/ single slave application

1. The NSS pin is configured as an input in this case.
2. In this configuration, the master's MISO pin and the slave's MOSI pin can be used as GPIOs.
Simplex communications
The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receive-
only using the RXONLY bit in the SPIx_CR2 register. In this configuration, only one line is
shift register
SPI clock
generator
Master
shift register
SPI clock
generator
Master
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
MISO
MOSI
SCK
(1)
NSS
Vcc
(2)
MISO
MOSI
SCK
(1)
NSS
Vcc
MISO
shift register
MOSI
SCK
(1)
NSS
Slave
MISO
shift register
(2)
MOSI
SCK
(1)
NSS
Slave
MS19827V1
MS19828V1
637/742