System Configuration Controller (Syscfg); Syscfg Registers; Syscfg Configuration Register 1 (Syscfg_Cfgr1) - STMicroelectronics STM32F05 series Reference Manual

RM0091
9

System configuration controller (SYSCFG)

The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
●
Enabling/disabling I
●
Remapping some DMA trigger sources from TIM16 and TIM17, USART1, and ADC to
different DMA channels
●
Remapping the memory located at the beginning of the code area
●
Managing the external interrupt line connection to the GPIOs
●
Managing robustness feature
9.1

SYSCFG registers

9.1.1

SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations on memory remap.
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the hardware
BOOT selection.
After reset these bits take the value selected by the BOOT pin (BOOT0) and by the option bit
(nBOOT1).
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and nBOOT1
option bit)
)
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
TIM17_
Res. Res. Res. DMA_
RMP
rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:16 I2C_PBx_FM+: Fast Mode Plus (FM+) driving capability activation bits.
Bits 15:13 Reserved, must be kept at reset value.
2
C Fast Mode Plus on some IO ports
27 26 25
Res. Res. Res.
11 10 9
USART1 USART1
TIM16_
_RX_ _TX_
DMA_
DMA_ DMA_
RMP
RMP RMP
rw rw rw
These bits are set and cleared by software. Each bit enables I
PB8, and PB9 I/Os.
0: PBx pin operates in standard mode.
2
1: I C FM+ mode enabled on PBx pin, and the Speed control is bypassed.
Doc ID 018940 Rev 1
System configuration controller (SYSCFG)
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
ADC_
DMA_ Res. Res. Res.
RMP
rw
20 19 18 17
I2C_ I2C_ I2C_
Res. PB9_ PB8_ PB7_
FM+ FM+ FM+
rw rw rw
4 3 2 1
Res. Res. Res. MEM_MODE
rw
2
C FM+ mode for PB6, PB7,
16
I2C_
PB6_
FM+
rw
0
rw
135/742