Inter-Integrated Circuit (I 2 C) Interface; I 2 C Introduction; I 2 C Main Features; Table 61. I2C Configurations In Goldfish And Manta Edge - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I
23 Inter-integrated circuit (I
2
23.1 I C introduction
2
The I C (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial I
bus-specific sequencing, protocol, arbitration and timing. It supports standard speed mode,
Fast Mode and Fast Mode Plus.
It is also SMBus (system management bus) and PMBus (power management bus)
compatible.
DMA can be used to reduce CPU overload.
2
23.2 I C main features
2
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I C bus specification rev03 compatibility:
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1-byte buffer with DMA capability
● Programmable analog and digital noise filters
The following additional features are also available depending on the product
implementation (see
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SMBus specification rev 2.0 compatibility:
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468/742
2
C) interface
2
Slave and master modes
Multimaster capability
Standard mode (up to 100 kHz)
Fast Mode (up to 400 kHz)
Fast Mode Plus (up to 1 MHz)
7-bit and 10-bit addressing mode
Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
All 7-bit addresses acknowledge mode
General call
Programmable setup and hold times
Easy to use event management
Optional clock stretching
Software reset
Section 23.3: I2C
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
Command and data acknowledge control
Address resolution protocol (ARP) support
Host and Device support
SMBus alert
Timeouts and idle condition detection
Doc ID 018940 Rev 1
2
C) interface
C bus. It provides multimaster capability, and controls all I
implementation):
RM0091
2
C