Baud Rate Register (Usart_Brr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bit 2 IRLP: IrDA low-power
This bit can only be written when the USART is disabled (UE=0).
Note: If IrDA mode is not supported, this bit is reserved and forced by hardware to '0'. Please
Bit 1 IREN: IrDA mode enable
This bit can only be written when the USART is disabled (UE=0).
Note: If IrDA mode is not supported, this bit is reserved and forced by hardware to '0'. Please
Bit 0 EIE: Error interrupt enable
25.7.4

Baud rate register (USART_BRR)

This register can only be written when the USART is disabled (UE=0). It may be automatically updated
by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000
31 30 29
Res Res Res
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 BRR[15:4]
Bits 3:0 BRR[3:0]
Universal synchronous asynchronous receiver transmitter (USART)
This bit is used for selecting between normal and low-power IrDA modes
0: Normal mode
1: Low-power mode
refer to Section 25.4: USART implementation on page
This bit is set and cleared by software.
0: IrDA disabled
1: IrDA enabled
refer to Section 25.4: USART implementation on page
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_ISR register).
0: Interrupt is inhibited
1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USART_ISR register.
28 27 26 25
Res Res Res Res
12 11 10 9
BRR[15:4]
rw rw rw rw
BRR[15:4] = USARTDIV[15:4]
When OVER8 = 0, BRR [3:0] = USARTDIV [3:0]
When OVER8 = 1, BRR [2:0] = USARTDIV [3:0] shifted 1 bit to the right. BRR [3] must be
kept cleared.
Doc ID 018940 Rev 1
24 23 22 21
Res Res Res Res
8 7 6 5
rw rw rw rw
573.
573.
20 19 18 17
Res Res Res Res
4 3 2 1
BRR[3:0]
rw rw rw rw
16
Res
0
rw
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