Comp Functional Description; General Description; Clock; Comparator Inputs And Output - STMicroelectronics STM32F05 series Reference Manual

Comparator (COMP)
14.3

COMP functional description

14.3.1

General description

The block diagram of the comparators is shown in

Figure 41. Comparators block diagram

PA4 (DAC1)
Bandgap
¾ Bandgap
½ Bandgap
¼ Bandgap
PA4 (DAC1)
Bandgap
¾ Bandgap
½ Bandgap
¼ Bandgap
14.3.2

Clock

The COMP clock provided by the clock controller is synchronous with the PCLK (APB
clock).
There is no clock enable control bit provided in the RCC controller.
Note: Important: The polarity selection logic and the output redirection to the port works
independently from the PCLK clock. This allows the comparator to work even in Stop mode.
14.3.3

Comparator inputs and output

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in "Alternate function mapping" table in the datasheet.
216/742
COMP1_INP
PA1
COMP1_INM
PA0
PA5
COMP2_INP
PA3
Window
mode
PA2
PA5
COMP2_INM
Doc ID 018940 Rev 1
Figure 41: Comparators block
+
COMP1
-
Polarity
selection
COMP2_OUT
+
COMP2
-
Polarity
selection
COMP1_OUT
PA0 /PA6 /PA11
COMP interrupt request
(to EXTI)
TIM1_BK1
TIM1_OCref_clr
TIM1_IC1
TIM2_IC4
TIM2_OCref_clr
TIM3_IC1
TIM3_OCref_clr
PA7 /PA2
COMP interrupt request
(to EXTI)
TIM1_BK1
TIM1_OCref_clr
TIM1_IC1
TIM2_IC4
TIM2_OCref_clr
TIM3_IC1
TIM3_OCref_clr
RM0091
diagram.
MS19824V1