Clock Configuration Register 3 (Rcc_Cfgr3) - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
7.4.13

Clock configuration register 3 (RCC_CFGR3)

Address: 0x30
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
31 30 29
Res Res Res
15 14 13
Res Res Res
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 ADCSW: ADC clock source selection
This bit is set and cleared by software to select ADC clock source.
0: HSI14 clock selected as ADC kernel clock (default)
1: PLCK divided by 2 or 4, selected as ADC clock
Note: When HSI14 is selected as ADC clock source, the HSI14 oscillator must not be
Bit 7 Reserved, must be kept at reset value.
Bit 6 CECSW: HDMI CEC clock source selection
This bit is set and cleared by software to select the CEC clock source.
0: HSI clock, divided by 244, selected as CEC clock (default)
1: LSE clock selected as CEC clock
Bit 5 Reserved, must be kept at reset value.
Bit 4 I2C1SW: I2C1 clock source selection
This bit is set and cleared by software to select the I2C1 clock source.
0: HSI clock selected as I2C1 clock source (default)
1: System clock (SYSCLK) selected as I2C1 clock
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 USART1SW[1:0]: USART1 clock source selection
This bit is set and cleared by software to select the USART1 clock source.
00: PCLK selected as USART1 clock source (default)
01: System clock (SYSCLK) selected as USART1 clock
10: LSE clock selected as USART1 clock
11: HSI clock selected as USART1 clock
114/742
28 27 26 25
Res Res Res Res
12 11 10 9
Res Res Res Res
disabled (HSI14DIS=0 in the
Doc ID 018940 Rev 1
24 23 22 21
Res Res Res Res
8 7 6 5
ADC CEC
Res Res
SW SW
rw rw
Clock control register 2
20 19 18 17
Res Res Res Res
4 3 2 1
I2C1
Res Res USART1SW[1:0]
SW
rw rw
(RCC_CR2)).
RM0091
16
Res
0
rw