Spi And I 2 S Registers; Spi Control Register 1 (Spix_Cr1) - STMicroelectronics STM32F05 series Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
26.7 SPI and I
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in
addition by can be accessed by 8-bit access.
26.7.1

SPI control register 1 (SPIx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
BIDI BIDI CRC CRC
MODE OE EN NEXT
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Bit 15 BIDIMODE: Bidirectional data mode enable
Note: This bit is not used in I
Bit 14 BIDIOE: Output enable in bidirectional mode
Note: 1. In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
Bit 13 CRCEN: Hardware CRC calculation enable
Note: 1. This bit should be written only when SPI is disabled (SPE = '0') for correct operation
Bit 12 CRCNEXT: Transmit CRC next
Note: 1. This bit has to be written as soon as the last data is written in the SPIx_DR register.
Bit 11 CRCL: CRC length
This bit is set and cleared by software to select the CRC length.
Note: 1. This bit should be written only when SPI is disabled (SPE = '0') for correct operation
Bit 10 RXONLY: Receive only
Note: This bit is not used in I
670/742
2
S registers
12 11 10 9
RX
CRCL SSM
ONLY
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0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
This bit combined with the BIDImode bit selects the direction of transfer in bidirectional mode
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
2. This bit is not used in I
0: CRC calculation disabled
1: CRC calculation Enabled
2. This bit is not used in I
0: Next transmit value is from Tx buffer
1: Next transmit value is from Tx CRC register
2. This bit is not used in I
0: 8-bit CRC length
1: 16-bit CRC length
2. This bit is not used in I
This bit combined with the BIDImode bit selects the direction of transfer in 2-line
unidirectional mode. This bit is also useful in a multislave system in which this particular
slave is not accessed, the output from the accessed slave is not corrupted.
0: Full duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
Doc ID 018940 Rev 1
8 7 6
LSB
SSI SPE
FIRST
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2
S mode
2
S mode
2
S mode
2
S mode
2
S mode
2
S mode
5 4 3 2
BR [2:0] MSTR
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RM0091
1 0
CPOL CPHA
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