Adc Control Register (Adc_Cr) - STMicroelectronics STM32F05 series Reference Manual

Analog-to-digital converter (ADC)
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
12.12.3

ADC control register (ADC_CR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
AD
Res. Res. Res.
CAL
rs
15 14 13 12
Res. Res. Res. Res.
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: Software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0,
ADSTP=0, ADDIS=0 and ADEN=0).
Bits 30:5 Reserved, must be kept at reset value.
194/742
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
Doc ID 018940 Rev 1
23 22 21
Res. Res. Res. Res.
7 6 5
AD
Res. Res. Res.
STP
RM0091
20 19 18 17
Res. Res. Res.
4 3 2 1
AD AD
Res.
START DIS
rs rs rs
16
Res.
0
AD
EN
rs