Tim16 And Tim17 Control Register 2 (Tim16_Cr2 And Tim17_Cr2) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bit 0 CEN: Counter enable
Note: External clock and gated mode can work only if the CEN bit has been previously set by
18.6.2

TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, always read as 0.
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bits 7:4 Reserved, always read as 0.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2 CCUS: Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
the COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, always read as 0.
Bit 0 CCPC: Capture/compare preloaded control
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.
0: Counter disabled
1: Counter enabled
software. However trigger mode can set the CEN bit automatically by hardware.
12 11 10 9
Res. Res. OIS1N
rw
(LOCK bits in TIMx_BKR register).
(LOCK bits in TIMx_BKR register).
Doc ID 018940 Rev 1
General-purpose timers (TIM15/16/17)
8 7 6 5
OIS1 Res. Res. Res.
rw
4 3 2 1
Res. CCDS CCUS Res.
rw rw
0
CCPC
rw
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