Adc On-Off Control (Aden, Addis, Adrdy); Figure 23. Adc Calibration - STMicroelectronics STM32F05 series Reference Manual

Analog-to-digital converter (ADC)
Software Procedure:
●
Ensure that ADEN=0
●
Set ADCAL=1
●
Wait until ADCAL=0
●
The calibration factor can be read from bits 6:0 of ADC_DR register

Figure 23. ADC calibration

ADCAL
ADC State
ADC_DR[6:0]
12.4.2

ADC on-off control (ADEN, ADDIS, ADRDY)

By default, the ADC is disabled and put in power-down mode (ADEN=0).
As shown in
converting accurately.
Two control bits are used to enable or disable the ADC:
●
Set ADEN=1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.
●
Set ADDIS=1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.
Conversion can then start either by setting SWSTART=1 (refer to
on external trigger and trigger polarity (EXTSEL, EXTEN) on page
trigger event occurs if triggers are enabled.
Follow this procedure to enable the ADC:
●
Set ADEN=1 in the ADC_CR register.
●
Wait until ADRDY=1 in the ADC_ISR register (ADRDY is set after the ADC startup
time). This can be handled by interrupt if the interrupt is enabled by setting the
ADRDYIE bit in the ADC_IER register.
172/742
OFF Startup
by S/W by H/W
Figure 24, the ADC needs a stabilization time of t
Doc ID 018940 Rev 1
t
CAB
CALIBRATE
0x00
RM0091
OFF
CALIBRATION
FACTOR
before it starts
STAB
Section 12.5: Conversion
178) or when an external