Ahb Peripheral Clock Enable Register (Rcc_Ahbenr) - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
Bit 14 SPI2RST: SPI2 reset
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 TIM14RST: TIM14 timer reset
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 TIM6RST: TIM6 timer reset
Bit 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3RST: TIM3 timer reset
Bit 0 TIM2RST: TIM2 timer reset
7.4.6

AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29
Res Res Res Res
15 14 13
Res Res Res Res
102/742
Set and cleared by software.
0: No effect
1: Reset SPI2
Set and cleared by software.
0: No effect
1: Reset window watchdog
Set and cleared by software.
0: No effect
1: Reset TIM14
Set and cleared by software.
0: No effect
1: Reset TIM6
Set and cleared by software.
0: No effect
1: Reset TIM3
Set and cleared by software.
0: No effect
1: Reset TIM2
28 27 26 25
Res Res Res
12 11 10 9
Res Res Res
Doc ID 018940 Rev 1
24 23 22 21
IOPFE
TSCEN Res Res
N
rw rw
8 7 6
CRCE
Res Res Res
N
rw
20 19 18
IOPD IOPC IOPB
EN EN EN
rw rw rw
5 4 3 2
FLITF SRAM
Res
EN EN
rw rw
RM0091
17 16
IOPA
Res
EN
rw
1 0
DMA
Res
EN
rw