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RM0091
Note:
Some of the I/O pins mentioned in the above register may not be available on small
packages.
9.1.5
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
EXTI15[3:0]
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 12 to 15)
Note:
Some of the I/O pins mentioned in the above register may not be available on small
packages.
9.1.6
SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x18
System reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
EXTI14[3:0]
rw
rw
rw
rw
These bits are written by software to select the source input for the EXTIx external
interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
other configurations: reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Doc ID 018940 Rev 1
System configuration controller (SYSCFG)
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
EXTI13[3:0]
rw
rw
rw
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
SRAM_
Res.
Res.
Res.
PEF
rc_w1
20
19
18
Res.
Res.
Res.
5
4
3
2
EXTI12[3:0]
rw
rw
rw
rw
20
19
18
Res.
Res.
Res.
5
4
3
2
PVD_
Res.
Res.
LOCK
rw
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
SRAM_
LOCUP
PARITY
_LOCK
_LOCK
rw
rw
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