Figure 201. Data Transmission - STMicroelectronics STM32F05 series Reference Manual

Inter-integrated circuit (I

Figure 201. Data transmission

SCL
Shift register
TXE
I2C_TXDR
Hardware transfer management
The I2C has a byte counter embedded in hardware in order to manage byte transfer and to
close the communication in various modes such as:
–
–
–
The byte counter is always used in master mode. By default it is disabled in slave mode, but
it can be enabled by software by setting the SBC (Slave Byte Control) bit in the I2Cx_CR2
register.
The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the
I2Cx_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255,
or if a receiver wants to control the acknowledge value of a received data byte, the reload
mode must be selected by setting the RELOAD bit in the I2Cx_CR2 register. In this mode,
TCR flag is set when the number of bytes programmed in NBYTES has been transferred,
and an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR
is cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be
cleared.
When RELOAD=0 in master mode, the counter can be used in 2 modes:
●
Automatic end mode (AUTOEND = '1' in the I2Cx_CR2 register). In this mode, the
master automatically sends a STOP condition once the number of bytes programmed
in the NBYTES[7:0] bit field has been transferred.
●
Software end mode (AUTOEND = '0' in the I2Cx_CR2 register). In this mode, software
action is expected once the number of bytes programmed in the NBYTES[7:0] bit field
has been transferred; the TC flag is set and an interrupt is generated if the TCIE bit is
set. The SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by
software when the START or STOP bit is set in the I2Cx_CR2 register. This mode must
be used when the master wants to send a RESTART condition.
478/742
2
C) interface
xx
data0
NACK, STOP and ReSTART generation in master mode
ACK control in slave receiver mode
PEC generation/checking when SMBus feature is supported
Doc ID 018940 Rev 1
ACK pulse
xx
wr data1 wr data2
data1
ACK pulse
xx
data2
RM0091
legend:
SCL
stretch
MS19849V1