STMicroelectronics STM32F05 series Reference Manual page 671

RM0091
Bit 9 SSM: Software slave management
Note: This bit is not used in I
Bit 8 SSI: Internal slave select
Note: This bit is not used in I
Bit 7 LSBFIRST: Frame format
Note: 1. This bit should not be changed when communication is ongoing.
Bit 6 SPE: SPI enable
Note: 1. This bit is not used in I
Bits 5:3 BR[2:0]: Baud rate control
Note: These bits should not be changed when communication is ongoing.
Bit 2 MSTR: Master selection
Note: 1. This bit should not be changed when communication is ongoing.
Bit1 CPOL: Clock polarity
Note: 1. This bit should not be changed when communication is ongoing.
Bit 0 CPHA: Clock phase
Note: 1. This bit should not be changed when communication is ongoing.
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the IO value of the NSS pin is ignored.
0: MSB transmitted first
1: LSB transmitted first
2. This bit is not used in I
0: Peripheral disabled
1: Peripheral enabled
2. When disabling the SPI, follow the procedure described in
SPI on page 644.
000: f /2
PCLK
001: f /4
PCLK
010: f /8
PCLK
011: f /16
PCLK
100: f /32
PCLK
101: f /64
PCLK
110: f /128
PCLK
111: f /256
PCLK
This bit is not used in I
0: Slave configuration
1: Master configuration
2. This bit is not used in I
0: CK to 0 when idle
1: CK to 1 when idle
2. This bit is not used in I
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
2. This bit is not used in I
Doc ID 018940 Rev 1
Serial peripheral interface / inter-IC sound (SPI/I2S)
2
S mode and SPI TI mode
2
S mode and SPI TI mode
2
S mode and SPI TI mode
2
S mode.
2
S mode.
2
S mode.
2
S mode and SPI TI mode
2
S mode and SPI TI mode
Procedure for disabling the
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