Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr) - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
Bit 0 DMAEN: DMA clock enable
Set and cleared by software.
0: DMA clock disabled
1: DMA clock enabled
7.4.7

APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB
domain is on going. In this case, wait states are inserted until the access to APB peripheral
is finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29
Res Res Res
15 14 13
USART1
Res Res
EN
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGMCUEN MCU debug module clock enable
Set and reset by software.
0: MCU debug module clock disabled
1: MCU debug module enabled
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM11 timer clock enable
Set and cleared by software.
0: TIM11 timer clock disabled
1: TIM11 timer clock enabled
Bit 17 TIM16EN: TIM10 timer clock enable
Set and cleared by software.
0: TIM10 timer clock disabled
1: TIM10 timer clock enabled
Bit 16 TIM15EN: TIM9 timer clock enable
Set and cleared by software.
0: TIM9 timer clock disabled
1: TIM9 timer clock enabled
Bit 15 Reserved, must be kept at reset value.
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28 27 26 25
Res Res Res Res
12 11 10 9
SPI1 TIM1 ADC
Res
EN EN EN
rw rw rw
Doc ID 018940 Rev 1
24 23 22 21
DBGM
Res Res Res
CUEN
rw
8 7 6 5
Res Res Res Res
20 19 18 17
TIM17 TIM16
Res Res
EN EN
rw rw
4 3 2 1
Res Res Res Res
RM0091
16
TIM15
EN
rw
0
SYSCFG
COMP
EN
rw