Figure 247. Transmission Using Dma - STMicroelectronics STM32F05 series Reference Manual

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Figure 247. Transmission using DMA

Idle preamble
TX line
TXE flag
DMA request
USART_DR
F1
TC flag
DMA writes
USART_DR
flag DMA TCIF
(Transfer complete)
software configures DMA writes F1
the DMA to send 3 into
data and enables the USART_DR
USART
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data is loaded from the USART_RDR register to a SRAM area configured using the DMA
peripheral (refer
whenever a data byte is received. To map a DMA channel for USART reception, use the
following procedure:
1. Write the USART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from USART_RDR to this memory area after each
RXNE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.en
Universal synchronous asynchronous receiver transmitter (USART)
Frame 1
set by hardware
cleared by DMA read
F2
set by hardware
DMA writes F2 DMA writes F3 The DMA transfer
into into
USART_DR USART_DR.
Section 10: Direct memory access controller (DMA) on page
Doc ID 018940 Rev 1
Frame 2
set by hardware
cleared by DMA read
F3
clear
by software
is complete
(TCIF=1 in
DMA_ISR)
Frame 3
set by hardware
ignored by the DMA
because DMA transfer is complete
software waits until TC=1
142)
set
by hardware
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