Figure 138. Counter Timing Diagram With Prescaler Division Change From 1 To 2; Figure 139. Counter Timing Diagram With Prescaler Division Change From 1 To 4 - STMicroelectronics STM32F05 series Reference Manual

RM0091
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 139
ratio is changed on the fly.

Figure 138. Counter timing diagram with prescaler division change from 1 to 2

Figure 139. Counter timing diagram with prescaler division change from 1 to 4

and Figure 140 give some examples of the counter behavior when the prescaler
CK_PSC
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
CK_PSC
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
Doc ID 018940 Rev 1
CEN
F7 F8 F9 FA FB FC
0
0
0
CEN
F7 F8 F9 FA FB FC
0
0
0
General-purpose timer (TIM14)
00 01 02 03
1
1
0 1 0 1 0 1 0 1
00 01
3
3
0 1 2 3 0 1 2 3
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