Control Register 3 (Usart_Cr3) - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
Table of Contents

Advertisement

Universal synchronous asynchronous receiver transmitter (USART)
25.7.3

Control register 3 (USART_CR3)

Address offset: 0x08
Reset value: 0x0000
31
30
29
Res
Res
Res
15
14
13
OVR
DEP
DEM
DDRE
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 WUFIE: Wakeup from Stop mode interrupt enable
Note: 1. WUFIE must be set before entering in Stop mode.
Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
Bits 19:17 SCARCNT[2:0]: Smartcard auto-retry count
Note: If Smartcard mode is not supported, this bit is reserved and forced by hardware to '0'.
Bit 16
618/742
28
27
26
25
Res
Res
Res
Res
12
11
10
9
ONE
CTSIE
CTSE
DIS
BIT
rw
rw
rw
rw
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever WUF=1 in the USART_ISR register
2. The WUF interrupt is active only in Stop mode.
3. If the USART does not support the wakeup from Stop feature, this bit is reserved
and forced by hardware to '0'.
This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag).
00: WUF active on address match (as defined by ADD[7:0] and ADDM7)
01:Reserved.
10: WUF active on Start bit detection
11: WUF active on RXNE.
This bit field can only be written when the USART is disabled (UE=0).
forced by hardware to '0'.
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
In transmission mode, it specifies the number of automatic retransmission retries, before
generating a transmission error (FE bit set).
In reception mode, it specifies the number or erroneous reception trials, before generating a
reception error (RXNE and PE bits set).
This bit field must be programmed only when the USART is disabled (UE=0).
When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to
stop retransmission.
0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1 to 0x7: number of automatic retransmission attempts (before signaling error)
Please refer to
Section 25.4: USART implementation on page
Reserved, must be kept at reset value.
Doc ID 018940 Rev 1
24
23
22
21
Res
Res
WUFIE
rw
rw
8
7
6
5
RTSE
DMAT
DMAR
SCEN
rw
rw
rw
rw
20
19
18
WUS[2:0]
SCARCNT2:0]
rw
rw
rw
4
3
2
HD
NACK
IRLP
SEL
rw
rw
rw
573.
RM0091
17
16
Res
rw
1
0
IREN
EIE
rw
rw

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32F05 series and is the answer not in the manual?

Subscribe to Our Youtube Channel

Table of Contents