Tim1 Event Generation Register (Tim1_Egr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
Bit 0 UIF: Update interrupt flag
15.4.6

TIM1 event generation register (TIM1_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
refer to CC1IF description
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
underflow (in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity)
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
–At overflow or underflow regarding the repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
–When CNT is reinitialized by a trigger event (refer to
control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
12 11 10 9
Res. Res. Res.
Doc ID 018940 Rev 1
8 7 6 5
Res. BG TG COMG
w w w
Advanced-control timers (TIM1)
Section 15.4.3: TIM1 slave mode
4 3 2
CC4G CC3G CC2G
w w w
1 0
CC1G UG
w w
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