Backup Domain Control Register (Rcc_Bdcr) - STMicroelectronics STM32F05 series Reference Manual

Reset and clock control (RCC)
7.4.9

Backup domain control register (RCC_BDCR)

Address offset: 0x20
Reset value: 0x0000 0018, reset by Backup domain Reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the
(RCC_BDCR)
protected and the DBP bit in the
these can be modified. Refer to
are only reset after a Backup domain Reset (see
internal or external Reset will not have any effect on these bits.
31 30 29
Res Res Res Res
15 14 13
RTC
Res Res Res
EN
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 32 used as RTC clock
Bits 7:5 Reserved, must be kept at reset value.
108/742
are in the Backup domain. As a result, after Reset, these bits are write-
28 27 26 25
Res Res Res
12 11 10 9
Res Res RTCSEL[1:0]
rw
Doc ID 018940 Rev 1
Power control register (PWR_CR)
Section 6.1.2 on page 75
Section 7.1.3: Backup domain
24 23 22
Res Res Res
8 7 6
Res Res
rw
Backup domain control register
has to be set before
for further information. These bits
21 20 19 18
Res Res Res Res
5 4 3 2
LSE
Res LSEDRV[1:0]
BYP
rw rw rw
RM0091
reset). Any
17 16
Res BDRST
rw
1 0
LSE
LSEON
RDY
r rw