Debug Mode; Figure 136. Triggering Timer 1 And 2 With Timer 1 Ti1 Input - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM2 and TIM3)
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.

Figure 136. Triggering timer 1 and 2 with timer 1 TI1 input

TIMER1-CEN=CNT_EN
TIMER 1-CK_PSC
TIMER2-CEN=CNT_EN
TIMER 2-CK_PSC
16.3.16

Debug mode

When the microcontroller enters debug mode (Cortex™-M0 core - halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBGMCU module.
328/742
CK_INT
TIMER 1-TI1
TIMER1-CNT
TIMER1-TIF
TIMER2-CNT
TIMER2-TIF
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