Tim2 And Tim3 Registers; Tim2 And Tim3 Control Register 1 (Tim2_Cr1 And Tim3_Cr1) - STMicroelectronics STM32F05 series Reference Manual

RM0091
16.4

TIM2 and TIM3 registers

Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
16.4.1

TIM2 and TIM3 control register 1 (TIM2_CR1 and TIM3_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, always read as 0.
Bits 9:8 CKD: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:5 CMS: Center-aligned mode selection
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
Bit 4 DIR: Direction
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
Bit 3 OPM: One-pulse mode
Section 1.1 on page 34
12 11 10 9
Res. Res. CKD[1:0]
rw
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
the counter is enabled (CEN=1)
0: Counter used as upcounter
1: Counter used as downcounter
mode.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
Doc ID 018940 Rev 1
General-purpose timers (TIM2 and TIM3)
for a list of abbreviations used in register descriptions.
8 7 6
ARPE CMS
rw rw rw
5 4 3 2
DIR OPM URS
rw rw rw rw
1 0
UDIS CEN
rw rw
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