Sw Protocol Sequence; Table 108. Packet Request (8-Bits); Table 109. Ack Response (3 Bits); Table 110. Data Transfer (33 Bits) - STMicroelectronics STM32F05 series Reference Manual

Debug support (DBG)
29.5.2

SW protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target

Table 108. Packet request (8-bits)

Bit
0
1
2
4:3
5
6
7
Refer to the Cortex-M0 TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.

Table 109. ACK response (3 bits)

Bit
0..2
The ACK Response must be followed by a turnaround time only if it is a READ transaction or
if a WAIT or FAULT acknowledge has been received.

Table 110. DATA transfer (33 bits)

Bit
0..31
32
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
722/742
Name
Start Must be "1"
0: DP Access
APnDP
1: AP Access
0: Write Request
RnW
1: Read Request
Address field of the DP or AP registers (refer to
A(3:2)
page
Parity Single bit parity of preceding bits
Stop 0
Not driven by the host. Must be read as "1" by the target
Park
because of the pull-up
Name
001: FAULT
ACK
010: WAIT
100: OK
Name
WDATA or
Write or Read data
RDATA
Parity
Single parity of the 32 data bits
Doc ID 018940 Rev 1
Description
725)
Description
Description
RM0091
Table 112 on