Gpio Port Configuration Lock Register (Gpiox_Lckr) (X = A..b - STMicroelectronics STM32F05 series Reference Manual

RM0091
8.4.8

GPIO port configuration lock register (GPIOx_LCKR) (x = A..B)

This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
LCK15 LCK14 LCK13 LCK12
rw rw rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset
occurs.
LOCK key write sequence:
WR LCKR[16] = '1' + LCKR[15:0]
WR LCKR[16] = '0' + LCKR[15:0]
WR LCKR[16] = '1' + LCKR[15:0]
RD LCKR
RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
These bits are read/write but can only be written when the LCKK bit is '0.
0: Port configuration not locked
1: Port configuration locked
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
LCK11 LCK10 LCK9
rw rw rw rw
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will
return '1' until the next CPU reset.
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
LCK8 LCK7 LCK6 LCK5
rw rw rw rw
General-purpose I/Os (GPIO)
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
LCK4 LCK3 LCK2 LCK1
rw rw rw rw
16
LCKK
rw
0
LCK0
rw
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