Universal Synchronous/Asynchronous Receiver/Transmitter (Usart); Table 6. Comparison Of I2C Analog And Digital Filters - STMicroelectronics STM32F038C6 Manual

Functional overview
Aspect
Pulse width of
suppressed spikes
Benefits
Drawbacks
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripheral can be served by the DMA controller.
7-bit addressing mode
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with extra output drive I/Os (up to 1 Mbit/s)
Independent clock
SMBus
Wakeup from STOP
1. X = supported.
3.14 Universal synchronous/asynchronous receiver/transmitter
(USART)
The device embeds one universal synchronous/asynchronous receiver/transmitter
(USART1) which communicates at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA
SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock
domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
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Table 6. Comparison of I
Analog filter
≥ 50 ns
Available in Stop mode
Variations depending on
temperature, voltage, process
Table 7. STM32F038x6 I
2
I C features
DocID026079 Rev 3
2
C analog and digital filters
Programmable length from 1 to 15
–Extra filtering capability vs.
standard requirements
–Stable length
Wakeup from Stop on address
match is not available when digital
2
C implementation
(1)
STM32F038x6
Digital filter
I2Cx peripheral clocks
filter is enabled.
I2C1
X
X
X
X
X
X
X
X