Clock Interrupt Register (Rcc_Cir) - STMicroelectronics STM32F05 series Reference Manual

RM0091
7.4.3

Clock interrupt register (RCC_CIR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res Res Res Res
15 14 13
HSI14 PLL
Res Res
RDYIE RDYIE
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
Bit 22
Bit 21 HSI14RDYC: HSI 14 MHz Ready Interrupt Clear
Bit 20 PLLRDYC: PLL ready interrupt clear
Bit 19 HSERDYC: HSE ready interrupt clear
Bit 18 HSIRDYC: HSI ready interrupt clear
Bit 17 LSERDYC: LSE ready interrupt clear
Bit 16 LSIRDYC: LSI ready interrupt clear
28 27 26 25
Res Res Res
12 11 10 9
HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw rw
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Reserved, must be kept at reset value.
This bit is set by software to clear the HSI14RDYF flag.
0: No effect
1: Clear HSI14RDYF flag
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Doc ID 018940 Rev 1
24 23 22 21
HSI14
Res CSSC Res
RDYC
w w
8 7 6 5
LSI HSI14
CSSF Res
RDYIE RDYF
rw r
Reset and clock control (RCC)
20 19 18
PLL HSE HSI
RDYC RDYC RDYC
w w w
4 3 2
PLL HSE HSI
RDYF RDYF RDYF
r r r r
17 16
LSE LSI
RDYC RDYC
w w
1 0
LSE LSI
RDYF RDYF
r r
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