Power Reset; Backup Domain Reset; Clocks - STMicroelectronics STM32F05 series Reference Manual

RM0091
Software reset
The SYSRESETREQ bit in Cortex-M0 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex™-M0 technical
reference manual for more details.
Low-power management reset
There are two ways to generate a low-power management reset:
1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
For further information on the User Option Bytes, refer to
Option byte loader reset
The option byte loader reset is generated when the FORCE_OBL bit (bit 13) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.
7.1.2

Power reset

A power reset is generated when one of the following events occurs:
1. Power-on/power-down reset (POR/PDR reset)
2. When exiting Standby mode
A power reset sets all registers to their reset values except the Backup domain
page 74)
7.1.3

Backup domain reset

The backup domain has two specific resets that affect only the backup domain
page 74).
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the
register
2. V
DD
7.2

Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):
●
HSI 8 MHZ RC oscillator clock
●
HSE oscillator clock
●
PLL clock
(RCC_BDCR).
or V power on, if both supplies have previously been powered off.
BAT
Doc ID 018940 Rev 1
Reset and clock control (RCC)
Section 4 on page 64.
Backup domain control
(Figure 6 on
(Figure 6 on
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