Adc Interrupt Enable Register (Adc_Ier) - STMicroelectronics STM32F05 series Reference Manual

RM0091
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by
software)
1: ADC is ready to start conversion
12.12.2

ADC interrupt enable register (ADC_IER)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 6:5 Reserved, must be kept at reset value.
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bit 3 EOSEQIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.
0: EOSEQ interrupt disabled
1: EOSEQ interrupt enabled. An interrupt is generated when the EOSEQ bit is set.
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
AWD
Res. Res. Res.
IE
rw
Analog-to-digital converter (ADC)
20 19 18
Res. Res. Res.
4 3 2
EOSEQ
OVRIE EOCIE
IE
rw rw rw
17 16
Res. Res.
1 0
EOSMP ADRDY
IE IE
rw rw
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