Flash Control Register (Flash_Cr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
3.5.5

Flash control register (FLASH_CR)

Address offset: 0x10
Reset value: 0x0000 0080
31 30 29
Res. Res. Res. Res.
15 14 13
FORCE_
Res. Res. EOPIE
OPTLOAD
rw
Bits 31:14 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
OPTWR
Res. ERRIE
E
rw rw rw
Bit 13 OBL_LAUNCH: Force option byte loading
When set to 1, this bit forces the option byte reloading. This operation generates
a system reset.
0: Inactive
1: Active
Bit 12 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR
register goes to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bit 11 Reserved, must be kept at reset value
Bit 10 ERRIE: Error interrupt enable
This bit enables the interrupt generation on an error when PGERR /
WRPRTERR are set in the FLASH_SR register.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bit 9 OPTWRE: Option bytes write enable
When set, the option bytes can be programmed. This bit is set on writing the
correct key sequence to the FLASH_OPTKEYR register.
This bit can be reset by software
Bit 8 Reserved, must be kept at reset value.
Bit 7 LOCK: Lock
Write to 1 only. When it is set, it indicates that the Flash is locked. This bit is reset
by hardware after detecting the unlock sequence.
In the event of unsuccessful unlock operation, this bit remains set until the next
reset.
Bit 6 STRT: Start
This bit triggers an ERASE operation when set. This bit is set only by software
and reset when the BSY bit is reset.
Bit 5 OPTER: Option byte erase
Option byte erase chosen.
Bit 4 OPTPG: Option byte programming
Option byte programming chosen.
Bit 3 Reserved, must be kept at reset value.
Doc ID 018940 Rev 1
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. LOCK STRT OPTER
rw rw rw
Embedded Flash memory
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
OPT
Res. MER PER
PG
rw rw rw
16
Res.
0
PG
rw
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