Figure 114. External Trigger Input Block; Figure 115. Control Circuit In External Clock Mode 2 - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM2 and TIM3)
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 114

Figure 114. External trigger input block

ETR pin
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

Figure 115. Control circuit in external clock mode 2

306/742
gives an overview of the external trigger input block.
ETR
0
divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR
TIMx_SMCR
CK_INT
CNT_EN
ETRP
ETRF
Counter clock = CK_CNT = CK_PSC
Counter register
Doc ID 018940 Rev 1
ETRP
filter
downcounter
CK_INT
ETF[3:0]
TIMx_SMCR
ETR
34
TI2F or
or
TI1F or
encoder
mode
external clock
TRGI
mode 1
ETRF external clock
mode 2
CK_INT
internal clock
mode
(internal clock)
ECE SMS[2:0]
TIMx_SMCR
35 36
RM0091
CK_PSC