Hdmi-Cec Interrupts; Table 105. Hdmi-Cec Interrupts - STMicroelectronics STM32F05 series Reference Manual

HDMI-CEC controller (HDMI-CEC)
Table 104. TXERR timing parameters (continued)
Time
T
n0
T
4
T
5
T
nf
T
6
28.6

HDMI-CEC interrupts

An interrupt can be produced:
●
during reception if a Receive Block Transfer is finished or if a Receive Error occurs.
●
during transmission if a Transmit Block Transfer is finished or if a Transmit Error occurs.

Table 105. HDMI-CEC interrupts

Rx-Byte Received
End of reception
Rx-Overrun
RxBit Rising Error
Rx-Short Bit Period Error
Rx-Long Bit Period Error
Rx-Missing Acknowledge Error
Arbitration lost
Tx-Byte Request
End of transmission
Tx-Buffer Underrun
Tx-Error
Tx-Missing Acknowledge Error
708/742
RXTOL ms
x 1.5
0 1.7
1 1.8
1 1.85
0 2.05
x 2.4
0 2.75
1 2.95
Interrupt event
Doc ID 018940 Rev 1
Description
The nominal time a device is permitted return to a
high impedance state (logical 0).
The latest time a device is permitted return to a high
impedance state (logical 0).
The earliest time for the start of a following bit.
The nominal data bit period.
The latest time for the start of a following bit.
Event flag
RXBR
RXEND
RXOVR
BRE
SBPE
LBPE
RXACKE
ARBLST
TXBR
TXEND
TXUDR
TXERR
TXACKE
RM0091
Enable Control bit
RXBRIE
RXENDIE
RXOVRIE
BREIE
SBPEIE
LBPEIE
RXACKEIE
ARBLSTIE
TXBRIE
TXENDIE
TXUDRIE
TXERRIE
TXACKEIE