Tim16 And Tim17 Break And Dead-Time Register; Tim17_Bdtr) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM15/16/17)
18.6.13 TIM16 and TIM17 break and dead-time register (TIM16_BDTR and

TIM17_BDTR)

Address offset: 0x44
Reset value: 0x0000
15 14 13
MOE AOE BKP BKE
rw rw rw
Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details
enable register (TIM15_CCER) on page
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 13 BKP: Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 12 BKE: Break enable
0: Break inputs (BRK and CCS clock failure event) disabled
1; Break inputs (BRK and CCS clock failure event) enabled
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
434/742
12 11 10 9
OSSR OSSI LOCK[1:0]
rw rw rw rw
in TIMx_BDTR register).
in TIMx_BDTR register).
TIMx_BDTR register).
Doc ID 018940 Rev 1
8 7 6 5
rw rw rw rw
(Section 18.5.8: TIM15 capture/compare
412).
4 3 2 1
DTG[7:0]
rw rw rw rw
RM0091
0
rw