Table 64. I2C-Smbus Specification Data Setup And Hold Times - STMicroelectronics STM32F05 series Reference Manual

RM0091
SDADEL <= {t
Note: -50 ns / -260 ns are part of the equation only when the analog filter is enabled.
Refer to
standard values.
●
After sending SDA output, SCL line is kept at low level during the setup time. This setup
time is
t
SCLDEL
In order to bridge the undefined region of the SDA transition (rising edge usually worst
case), you must program SCLDEL in such a way that:
Refer to
standard values.
Table 64.
t (us)
HD;DAT
t (ns)
SU;DAT
tr(ns)
t (ns)
f
Additionally, in master mode, the SCL clock high and low levels must be configured by
programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2Cx_TIMINGR register.
●
When the SCL falling edge is internally detected, a delay is inserted before releasing
the SCL output. This delay is
t
I2CCLK.
t
SCLL
●
When the SCL rising edge is internally detected, a delay is inserted before forcing the
SCL output to low level. This delay is
(PRESC+1) x t
Refer to section
Caution: Changing the timing configuration is not allowed when the I2C is enabled.
I2C configuration
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral.
Refer to
Caution: Changing the NOSTRETCH configuration is not allowed when the I2C is enabled.
HD;DAT (max)
Table 64.: I2C-SMBUS specification data setup and hold times
t = (SCLDEL+1) x t
SCLDEL
impacts the setup time
{[t + t
r (max) SU;DAT (min)
Table 64.: I2C-SMBUS specification data setup and hold times
I2C-SMBUS specification data setup and hold times
Parameter
Data hold time
Data setup time
rise time of
both SDA and
SCL signals
fall time of
both SDA and
SCL signals
impacts the SCL low time
t
I2CCLK. SCLH
: I2C master initialization
: I2C slave initialization
Doc ID 018940 Rev 1
-260 ns - [(DNF+3) x t
where
t
PRESC PRESC
t
SU;DAT .
] / [
(PRESC+1)] x t
Standard Fast Mode
Min. Max Min.
0 3.45 0
250 100
1000
300
t = (SCLL+1) x t
SCLL
t
LOW .
t = (SCLH+1) x t
SCLH
impacts the SCL high time
for more details.
for more details.
Inter-integrated circuit (I
]} / {(PRESC +1) x t
I2CCLK
for t
= (PRESC+1) x t
I2CCLK.
]} - 1 <=
SCLDEL
I2CCLK
for t
Fast Mode
Plus
Max Min. Max
0.9 0 0.45
50
300 120
300 120
where
t = (PRESC+1) x
PRESC PRESC
where
PRESC
t
HIGH .
2
C) interface
}
I2CCLK
and t
f HD;DAT
and t
r SU;DAT
SMBUS
Min. Max
300
250
1000
300
t =
PRESC
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