Tsc I/O Analog Switch Control Register (Tsc_Ioascr); Tsc I/O Sampling Control Register (Tsc_Ioscr) - STMicroelectronics STM32F05 series Reference Manual

RM0091
27.6.6

TSC I/O analog switch control register (TSC_IOASCR)

Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 Gx_IOy: Gx_IOy analog switch enable
These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
0: Gx_IOy analog switch disabled (opened)
1: Gx_IOy analog switch enabled (closed)
Note: These bits control the I/O analog switch whatever the I/O control mode is (even if
27.6.7

TSC I/O sampling control register (TSC_IOSCR)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 Gx_IOy: Gx_IOy sampling mode
These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor
I/O. Only one I/O per analog I/O group must be defined as sampling capacitor.
0: Gx_IOy unused
1: Gx_IOy used as sampling capacitor
Note: These bits must not be modified when an acquisition is on-going.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
controlled by standard GPIO registers).
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.
Doc ID 018940 Rev 1
24 23 22 21
Res. G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw
8 7 6 5
rw rw rw rw
24 23 22 21
Res. G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw
8 7 6 5
rw rw rw rw
Touch sensing controller (TSC)
20 19 18
rw rw rw
4 3 2
rw rw rw
20 19 18
rw rw rw
4 3 2
rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
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