Dac Output Voltage; Dac Trigger Selection; Table 40. External Triggers; Figure 40. Timing Diagram For Conversion With Trigger Disabled Ten = 0 - STMicroelectronics STM32F05 series Reference Manual

Digital-to-analog converter (DAC1)

Figure 40. Timing diagram for conversion with trigger disabled TEN = 0

APB1_CLK
13.3.5

DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and VDDA.
The analog output voltages on each DAC channel pin are determined by the following
equation:
DACoutput
13.3.6

DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possi-
ble events will trigger conversion as shown in
Table 40.
Timer 6 TRGO event
Timer 3TRGO event
Reserved
Timer 15 TRGO event
Timer 2 TRGO event
Reserved
EXTI line9
SWTRIG
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
208/742
DHR 0x1AC
DOR
DOR
×
= V ------------- -
DDA
4095
External triggers
Source
Internal signal from on-chip
timers
External pin
Software control bit
Doc ID 018940 Rev 1
0x1AC
t
SETTLING
Table 40.
Type
RM0091
Output voltage
available on DAC_OUT pin
ai14711b
TSEL[2:0]
000
001
010
011
100
101
110
111