Tim14 Capture/Compare Mode Register 1 (Tim14_Ccmr1) - STMicroelectronics STM32F05 series Reference Manual

General-purpose timer (TIM14)
17.4.5

TIM14 capture/compare mode register 1 (TIM14_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15 14 13
Res. Res. Res. Res.
Res. Res. Res. Res.
Output compare mode
Bits 15:7
Bits 6:4 OC1M: Output compare 1 mode
Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison
Bit 3 OC1PE: Output compare 1 preload enable
Note: The PWM mode can be used without validating the preload register only in one pulse
Bit 2 OC1FE: Output compare 1 fast enable
368/742
12 11 10 9
Res. Res. Res.
Res. Res. Res.
Reserved
These bits define the behavior of the output reference signal OC1REF from which OC1 is
derived. OC1REF is active high whereas OC1 active level depends on CC1P bit.
000: Frozen. The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.
111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.
changes or when the output compare mode switches from frozen to PWM mode.
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then
set to the compare level independently of the result of the comparison. Delay to sample the
trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the
channel is configured in PWM1 or PWM2 mode.
Doc ID 018940 Rev 1
8 7 6 5
Res. Res. OC1M[2:0]
Res. IC1F[3:0]
rw rw rw
4 3 2 1
OC1PE OC1FE
CC1S[1:0]
IC1PSC[1:0]
rw rw rw rw
RM0091
0
rw