Programmable Data Width, Data Alignment And Endians; Table 23. Programmable Data Width & Endian Behavior (When Bits Pinc = Minc = 1) - STMicroelectronics STM32F05 series Reference Manual

Direct memory access controller (DMA)
10.3.4

Programmable data width, data alignment and endians

When PSIZE and MSIZE are not equal, the DMA performs some data alignments as
described in
MINC = 1).
Table 23. Programmable data width & endian behavior (when bits PINC = MINC = 1)
Number
Source of data
Destination
port items to
port width
width transfer
(NDT)
8 8 4
8 16 4
8 32 4
16 8 4
16 16 4
16 32 4
32 8 4
32 16 4
32 32 4
Addressing an AHB peripheral that does not support byte or halfword write
operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on
the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does
not support byte or halfword write operations (when HSIZE is not used by the peripheral)
146/742
Table 23: Programmable data width & endian behavior (when bits PINC =
Source content:
address / data
@0x0 / B0 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0
@0x1 / B1 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1
@0x2 / B2 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2
@0x3 / B3 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3
@0x0 / B0 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0
@0x1 / B1 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2
@0x2 / B2 3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4
@0x3 / B3 4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6
@0x0 / B0 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0
@0x1 / B1 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4
@0x2 / B2 3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8
@0x3 / B3 4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC
@0x0 / B1B0 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0
@0x2 / B3B2 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1
@0x4 / B5B4 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2
@0x6 / B7B6 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3
@0x0 / B1B0 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0
@0x2 / B3B2 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2
@0x4 / B5B4 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4
@0x6 / B7B6 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6
@0x0 / B1B0 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0
@0x2 / B3B2 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4
@0x4 / B5B4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8
@0x6 / B7B6 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC
@0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0
@0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1
@0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2
@0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3
@0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0
@0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1
@0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2
@0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3
@0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0
@0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4
@0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8
@0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC
Doc ID 018940 Rev 1
Transfer operations
RM0091
Destination
content:
address / data
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3
@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3
@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6
@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC