STMicroelectronics STM32F05 series Reference Manual page 691

RM0091
Bit 15 SSPSC: Spread spectrum prescaler
Note: This bit must not be modified when an acquisition is on-going.
Bits 14:12 PGPSC[2:0]: pulse generator prescaler
Note: These bits must not be modified when an acquisition is on-going.
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:5 MCV[2:0]: Max count value
Note: These bits must not be modified when an acquisition is on-going.
Bit 4 IODEF: I/O Default mode
Note: This bit must not be modified when an acquisition is on-going.
Bit 3 SYNCPOL: Synchronization pin polarity
Bit 2 AM: Acquisition mode
Note: This bit must not be modified when an acquisition is on-going.
This bit is set and cleared by software. It selects the AHB clock divider used to generate the
spread spectrum clock (f
0: f
HCLK
1: f /2
HCLK
These bits are set and cleared by software.They select the AHB clock divider used to
generate the pulse generator clock (f
000: f
HCLK
001: f /2
HCLK
010: f /4
HCLK
011: f /8
HCLK
100: f /16
HCLK
101: f /32
HCLK
110: f /64
HCLK
111: f /128
HCLK
These bits are set and cleared by software. They define the maximum number of charge
transfer pulses that can be generated before a max count error is generated.
000: 255
001: 511
010: 1023
011: 2047
100: 4095
101: 8191
110: 16383
111: reserved
This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when
there is no on-going acquisition. When there is an on-going acquisition, it defines the
configuration of all unused IOs (not defined as sampling capacitor I/O or as channel I/O).
0: I/Os are forced to output push-pull low
1: I/Os are in input floating
This bit is set and cleared by software to select the polarity of the synchronization input pin.
0: Falling edge only
1: Rising edge and high level
This bit is set and cleared by software to select the acquisition mode.
0: Normal acquisition mode (acquisition starts as soon as START bit is set)
1: Synchronized acquisition mode (acquisition starts if START bit is set and when the
selected signal is detected on the SYNC input pin)
Doc ID 018940 Rev 1
).
SSCLK
).
PGCLK
Touch sensing controller (TSC)
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