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RM0091
5.4.3
Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept cleared.
Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 Reserved, must be kept cleared.
Bits 4:3 These bits are generated only if the generic "full_poly" = 1 otherwise they are forced to 0
Bits 2:1 Reserved, must be kept cleared.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the value stored
in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Doc ID 018940 Rev 1
Cyclic redundancy check calculation unit (CRC)
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
REV_O
Res.
REV_IN[1:0]
UT
rw
rw
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
16
Res.
0
RESET
rs
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