Figure 60. Counter Timing Diagram, Internal Clock Divided By N; Figure 61. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow) - STMicroelectronics STM32F05 series Reference Manual

Advanced-control timers (TIM1)

Figure 60. Counter timing diagram, internal clock divided by N

Figure 61. Counter timing diagram, update event with ARPE=1 (counter underflow)

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CK_PSC
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
Doc ID 018940 Rev 1
20
1F 01
06 05 04 03 02 01 00 01 02 03 04 05 06 07
FD
FD
RM0091
00
36
36