Spi Status Register (Spix_Sr) - STMicroelectronics STM32F05 series Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
Bit 2 SSOE: SS output enable
Note: This bit is not used in I
Bit 1 TXDMAEN: Tx buffer DMA enable
Bit 0 RXDMAEN: Rx buffer DMA enable
26.7.3

SPI status register (SPIx_SR)

Address offset: 0x08
Reset value: 0x0002
15 14 13
Res. Res. Res.
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:11 FTLVL[1:0]: FIFO Transmission Level
These bits are set and cleared by hardware.
Note: These bits are not used in I²S mode
Bits 10:9 FRLVL[1:0]: FIFO reception level
Note: These bits are not used in I²S mode and in SPI receive-only mode while CRC
Bits 8 FRE: Frame format error
674/742
0: SS output is disabled in master mode and the SPI interface can work in multimaster
configuration
1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI
interface cannot work in a multimaster environment.
When this bit is set, a DMA request is generated whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
When this bit is set, a DMA request is generated whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled
12 11 10 9
FTLVL[1:0] FRLVL[2:0]
r r r r
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2)
These bits are set and cleared by hardware.
00: FIFO empty
01: 1/4 FIFO
10: 1/2 FIFO
11: FIFO full
calculation is enabled.
This flag is used for SPI in TI slave mode and I
error flags and Section 26.6.7: I2S error
This flag is set by hardware and reset when SPIx_SR is read by software.
0: No frame format error
1: A frame format error occurred
Doc ID 018940 Rev 1
2
S mode and SPI TI mode
8 7 6
FRE BSY OVR MODF
r r r
2
S slave mode. Refer to
flags.
5 4 3 2
CRC CHSID
UDR
ERR E
r rc_w0 r r
Section 26.3.9: SPI
RM0091
1 0
TXE RXNE
r r