STMicroelectronics STM32F05 series Reference Manual page 613

RM0091
Bit 6 TCIE: Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever TC=1 in the USART_ISR register
Bit 5 RXNEIE: RXNE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_ISR register
Bit 4 IDLEIE: IDLE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: 1: During transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: USART enable in Stop mode
When this bit is cleared, the USART is not able to wake up the MCU from Stop mode.
When this bit is set, the USART is able to wake up the MCU from Stop mode, provided that
the USART clock selection is HSI or LSE in the RCC.
This bit is set and cleared by software.
0: USART not able to wake up the MCU from Stop mode.
1: USART able to wake up the MCU from Stop mode. When this function is active, the clock
source for the USART must be HSI or LSE (see RCC chapter)
Note: 1: It is recommended to set the UESM bit just before entering Stop mode and clear it on
Bit 0 UE: USART enable
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the USART is kept, but all the status
flags, in the USART_ISR are reset. This bit is set and cleared by software.
0: USART prescaler and outputs disabled, low power mode
1: USART enabled
Note: 1: In order to go into low power mode without generating errors on the line, the TE bit
Universal synchronous asynchronous receiver transmitter (USART)
(idle line) after the current word, except in Smartcard mode. In order to generate an idle
character, the TE must not be immediately written to 1. In order to ensure the required
duration, the software can poll the TEACK bit in the USART_ISR register.
2: When TE is set there is a 1 bit-time delay before the transmission starts.
exit from Stop mode.
2: If the USART does not support the wakeup from Stop feature, this bit is reserved and
forced by hardware to '0'. Please refer to
page 573.
must be reset before and the software must wait for the TC bit in the USART_ISR to be
set before resetting the UE bit.
2: The DMA requests are also reset when UE = 0 so the DMA channel must be
disabled before resetting the UE bit.
Doc ID 018940 Rev 1
Section 25.4: USART implementation on
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