Tim15 Dma Address For Full Transfer (Tim15_Dmar); Tim15 Register Map; Table 55. Tim15 Register Map And Reset Values - STMicroelectronics STM32F05 series Reference Manual

General-purpose timers (TIM15/16/17)
18.5.17

TIM15 DMA address for full transfer (TIM15_DMAR)

Address offset: 0x4C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
18.5.18

TIM15 register map

TIM15 registers are mapped as 16-bit addressable registers as described in the table below:
Table 55. TIM15 register map and reset values
Offset Register
TIM15_CR1
0x00
Reset value
TIM15_CR2
0x04
Reset value
TIM15_SMCR
0x08
Reset value
TIM15_DIER
0x0C
Reset value
TIM15_SR
0x10
Reset value
TIM15_EGR
0x14
Reset value
TIM15_CCMR1
Output compare
mode
Reset value
0x18
TIM15_CCMR1
Input capture
mode
Reset value
TIM15_CCER
0x20
Reset value
TIM15_CNT
0x24
Reset value
420/742
12 11 10 9
rw rw rw rw
(TIMx_CR1 address) + (DBA + DMA index) x 4
Doc ID 018940 Rev 1
8 7 6 5
DMAB[15:0]
rw rw rw rw
0
OC2M
[2:0]
0 0
IC2F[3:0]
0 0 0
0 0 0
4 3 2
rw rw rw
CKD
[1:0]
0 0 0
MMS[2:0]
0 0 0 0 0 0
TS[2:0]
0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
0 0 0
CC2S OC1M
[1:0] [2:0]
0 0 0 0 0 0 0 0
IC2
CC2S
PSC IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0 0
0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0
RM0091
1 0
rw rw
0 0 0 0
0 0 0
SMS[2:0]
0 0 0
0 0 0
0 0 0
0 0 0
CC1S
[1:0]
0 0 0 0
IC1
CC1S
PSC
[1:0]
[1:0]
0 0 0 0
0 0 0 0
0 0 0 0