Syscfg External Interrupt Configuration Register 2; (Syscfg_Exticr2); (Syscfg_Exticr3) - STMicroelectronics STM32F05 series Reference Manual

Advanced arm-based 32-bit mcus
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System configuration controller (SYSCFG)
9.1.3

SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)

Address offset: 0x0C
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
EXTI7[3:0]
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 4 to 7)
Note:
Some of the I/O pins mentioned in the above register may not be available on small
packages.
9.1.4
SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)

Address offset: 0x10
Reset value: 0x0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
EXTI11[3:0]
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 8 to 11)
138/742
28
27
26
25
Res.
Res.
Res.
12
11
10
9
EXTI6[3:0]
rw
rw
rw
rw
These bits are written by software to select the source input for the EXTIx
external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: reserved
x100: reserved
x101: PF[x] pin
other configurations: reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
EXTI10[3:0]
rw
rw
rw
rw
These bits are written by software to select the source input for the EXTIx
external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
other configurations: reserved
Doc ID 018940 Rev 1
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
EXTI5[3:0]
rw
rw
rw
rw
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
EXTI9[3:0]
rw
rw
rw
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
EXTI4[3:0]
rw
rw
rw
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
EXTI8[3:0]
rw
rw
rw
rw
RM0091
16
Res.
0
rw
16
Res.
0
rw

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