System Clock (Sysclk) Selection; Clock Security System (Css); Adc Clock - STMicroelectronics STM32F05 series Reference Manual

RM0091
The LSIRDY flag in the
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the
7.2.6

System clock (SYSCLK) selection

Three different clock sources can be used to drive the system clock (SYSCLK):
●
HSI oscillator
●
HSE oscillator
●
PLL
After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source becomes ready. Status bits in the
Clock control register (RCC_CR)
currently used as a system clock.
7.2.7

Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1) and general-
purpose timers (TIM15, TIM16 and TIM17) and an interrupt is generated to inform the
software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to
perform rescue operations. The CSSI is linked to the Cortex-M0 NMI (Non-Maskable
Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the HSE
oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock
when the failure occurs, the PLL is disabled too.
7.2.8

ADC clock

The ADC clock is either the dedicated 14 MHz RC oscillator (HSI14) or PCLK divided by 2
or 4. When the ADC clock is derived from PCLK, it is in an opposite phase with PCLK. The
14 MHz RC oscillator can be configured by software either to be turned on/off ("auto-off
mode") by the ADC interface or to be always enabled. The HSI 14 MHz RC oscillator cannot
be turned on by ADC interface when the APB clock is selected as kernel clock.
Control/status register (RCC_CSR)
Clock interrupt register
indicate which clock(s) is (are) ready and which clock is
Clock interrupt register
Doc ID 018940 Rev 1
Reset and clock control (RCC)
indicates if the LSI oscillator is
(RCC_CIR).
(RCC_CIR).
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